The Most Essential Factor for High-Speed, Low-Power 0.35 µm Complementary Metal-Oxide-Semiconductor Circuits Fabricated on Separation-by-Implanted-Oxygen (SIMOX) Substrates
In: Japanese Journal of Applied Physics, Jg. 36 (1997-11-01), S. 6699-6699
Online
unknown
Zugriff:
We present experimental data concerning the propagation delay time and the power consumption of 0.35 µ m complementary metal-oxide-semiconductor (CMOS) gates (inverter, NAND, NOR) fabricated on the commercial standard high dose separation-by-implanted-oxygen (SIMOX) substrates. Each CMOS gate was composed of the fully depleted (FD) mode N- and P-type metal-oxide-semiconductor (NMOS and PMOS) transistors or the partially depleted (PD) mode ones with no body-contact. On the basis of the experimental data, together with SPICE simulation results, we show that the FD-mode is not the primary factor for high-speed, low-power performances of the CMOS/SIMOX circuits, but the reduced drain parasitic capacitance (both the bottom and the peripheral components) with the thin film silicon-on-insulator (SOI) structure is. Furthermore, we show the significance of the design and control of the transistor threshold voltage and/or the off-state leakage current for high-speed, low-power CMOS/SIMOX circuits.
Titel: |
The Most Essential Factor for High-Speed, Low-Power 0.35 µm Complementary Metal-Oxide-Semiconductor Circuits Fabricated on Separation-by-Implanted-Oxygen (SIMOX) Substrates
|
---|---|
Autor/in / Beteiligte Person: | Yoshino, Akira ; Hamatake, Nobuhisa ; Okumura, Koichiro ; Kumagai, Kouichi ; Kurosawa, Susumu |
Link: | |
Zeitschrift: | Japanese Journal of Applied Physics, Jg. 36 (1997-11-01), S. 6699-6699 |
Veröffentlichung: | IOP Publishing, 1997 |
Medientyp: | unknown |
ISSN: | 1347-4065 (print) ; 0021-4922 (print) |
DOI: | 10.1143/jjap.36.6699 |
Schlagwort: |
|
Sonstiges: |
|